1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor memory device of the type of static random access memory (SRAM) and a method of fabricating the same.
2. Description of the Prior Art
There has been known SRAM as a type of semiconductor memory device. The SRAM is advantageous in that it does not need the refreshing operation and retains data stably.
FIG. 34 shows the equivalent circuit of a typical SRAM-type memory cell having a high-resistance load. This memory cell consists of a pair of driver transistors Q1 and Q2, a pair of access transistors Q3 and Q4, and a pair of high-resistance load resistors R1 and R2. The load resistors R1 and R2 have their one ends connected to the power source Vcc and their other ends connected to memory nodes N1 and N2, respectively.
The driver transistors and access transistors Q1-Q4 are MOS (Metal Oxide Semiconductor) transistors. The driver transistors Q1 and Q2 have their source regions connected to the ground (GND) voltage, their drain regions connected to the memory nodes N1 and N2, respectively, and their gate electrodes connected to the memory nodes N2 and N1, respectively.
The access transistor Q3 has its one of two source/drain regions connected to the memory node N1 and its other source/drain region connected to a bit line. Similarly, the access transistor Q4 has its one of two source/drain regions connected to the memory node N2 and its other source/drain region connected to another bit line. The access transistors Q3 and Q4 have their gate electrodes connected to a word line.
In regard to SRAM-type semiconductor memory devices, such as the one mentioned above, Japanese patent publication JP-A-3-83289 discloses a semiconductor structure in which MOS transistors of a memory cell (will be termed "memory transistor " hereinafter) have their threshold voltage set higher than that of MOS transistors of a peripheral circuit (will be termed "peripheral transistor " hereinafter).
Referring to FIG. 35 showing the cross section of the semiconductor memory device disclosed in the above-mentioned patent publication, in a memory cell area on the major surface of a p-type semiconductor substrate 501, there is formed an n-well 503. There is further formed a p-well 505 within the area of the n-well 503 on the major substrate surface. On the surface of the p-well 505, an n-MOS transistor 510 having a pair of n-type source/drain regions 511 and a gate electrode layer 515 is formed.
In a peripheral circuit area on the major surface of the p-type semiconductor substrate 501, there is formed a p-well 507. On the surface of the p-well 507, an n-MOS transistor 530 having a pair of n-type source/drain regions 531 and a gate electrode layer 535 is formed.
The p-well 505 of the memory cell area has the application of a source-well reverse bias voltage provided by a substrate bias voltage generation circuit 545. Based on this reverse bias voltage application, in the semiconductor memory device of the above-mentioned patent publication, the memory transistor 510 has its threshold voltage set higher than that of the peripheral transistor 530 so that the memory cell drive current is smaller and the peripheral circuit provides a larger drive current.
Consequently, the normal data retention in memory cells is ensured and the operation of peripheral circuits including the input/output buffer, decoder and word driver is sped up.
The semiconductor memory device shown in FIG. 35 is fabricated conventionally in the sequential steps of process as shown in the cross-sectional diagrams of FIG. 36 through FIG. 40.
Referring to FIG. 36, in a peripheral circuit area on a p-type semiconductor substrate 501, a resist pattern 551a is formed based on the usual photolithographic process. By using the resist pattern 551a as a mask, n-type impurity such as phosphor (P) is doped to form an n-type region 503a in the memory cell area. The resist pattern 551a is removed thereafter.
Referring to FIG. 37, the n-type region 503a is diffused into the substrate 501 based on the heat treatment, and an n-well 503 is formed in the memory cell area.
Referring to FIG. 38, a resist pattern 551b is formed based on the photolithographic process. By using the resist pattern 551b as a mask, p-type impurity such as boron (B) is doped selectively to form p-type regions 505a and 507a where a memory transistor and peripheral transistor will be formed, respectively. The resist pattern 551b is removed thereafter.
Referring to FIG. 39, the p-type regions 505a and 507a are diffused based on the heat treatment, and a p-well 505 is formed in the n-well 503 and another p-well 507 is formed in the peripheral circuit area.
Referring to FIG. 40, a device separation insulating layer 541 is formed based on the usual LOCOS (Local Oxidation of Silicon) process or the like. Silicon oxide films 514 which will become gate oxide films are formed based on the heat treatment or the like. P-type impurity such as boron for determining the threshold voltage is doped to the entire surface.
After that, the transistors and the bias voltage generation circuit are formed to complete the semiconductor memory device shown in FIG. 35.
The conventional semiconductor memory device uses the bias voltage generation circuit 545 for making the threshold voltage different between the memory transistor 510 and peripheral transistor 530, and this circuit takes an extra area on the chip. As a result, the chip size increases, making the device unsuitable for high-density integration, the device cost rises, and the power consumption increases due to the provision of the bias voltage generation circuit 545.
In addition, the power voltage added by the absolute value of the substrate bias voltage is applied to the gate oxide film of the memory transistor 510, e.g., for a power voltage of 5 V and a substrate bias voltage of -3 V, a total of 8 V is applied to the gate oxide film. The higher application voltage to the gate oxide film adversely affects its life time. The decay of gate oxide film is more pronounced for lower power voltage ratings. Specifically, with the substrate bias voltage of -3 V being applied, when the power voltage is 5 V, the gate oxide film has the application of 8 V, as mentioned above, which is 1.6 times the power voltage. If the power voltage is 3 V, the gate oxide film has the application of 6 V, which is twice the power voltage.
Accordingly, the conventional semiconductor memory device is deficient in that it is not suitable for high-density integration, it consumes much power, and its gate oxide film decays quickly.
In addition, the conventional fabrication method of semiconductor memory device is deficient in that it includes intricate steps of process for forming the substrate bias voltage generation circuit.